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Synthesis, Place & Route
Ketan Joshi
Director of Marketing, SP&R
Design Concept to Implementation
Design Implementation Plan
Productive Design Plan with Cadence SP&R
Productive Design Plan with Cadence SP&R
Productive Design Plan with Cadence SP&R
Ambit BuildGates Quick Reference Card
What is it?
A logic synthesis tool
Like conventional synthesis, with greater performance and capacity
Who is the Typical User?
Logic designers using ASIC or COT flows
Why is it Better?
Higher performance/capacity
Superior QoR
Integrated Static Timing sign-off
Integrated Chip Synthesis and STA
Ambit BuildGates: Comprehensive Synthesis
Verilog, VHDL, EDIF
Integrated, Sign-off timing engine
Time Budgeting
Graphical UI
Distributed synthesis
AmbitWare
Test Synthesis
TCL - user interface
SDF,GCF, PDEF
Sun, HP, IBM
Business StatisticsConventional Synthesis
Over 500 customers
More than 3000 active licenses worldwide
Leading ASIC vendor support
AMI, Atmel, Chip Express, Faraday Technology, Fujitsu, IBM, Kawasaki Steel, LSI, Lucent, Matsushita, Mitsubishi, NEC, OKI, Toshiba, VLSI
Productive Design Plan with Cadence SP&R
Low Power Synthesis OptionQuick Reference Card
What is it?
An option to Ambit BuildGates and PKS
Enables less power consuming design
Who is the Typical User?
Logic designers using ASIC or COT flows;
Battery powered applications, consumer electronics
Why is it Better?
Integrated, single tool solution
Superior power savings
Faster runtime
Low Power Synthesis Option
RTL and gate level optimizations
Auto clock gating
Sleep-mode for modules, components
Fully design-constraint driven
Accurate -- RTL transformations based on gate level timing/power
Power analysis
Integrated transparently
Customer Benchmark Data
Significant power savings over conventional flows
Customer 1: 48% power reduction
Customer 2: 58% power reduction
Better timing, area, and power numbers than competitors
Customer 2: 8.3% better power; 5.6% smaller area; better slack
Customer 3: 14.99% better power; 6x faster runtime; similar area, slack
Productive Design Plan with Cadence SP&R
Datapath Synthesis Option Quick Reference Card
What is it?
An option to Ambit BuildGates and PKS
Enables faster design, smaller area
Who is the Typical User?
Logic designers using ASIC or COT flows
DSP, multimedia, telecom, networking, processor
Why i it Better?
Integrated, single tool solution
Superior timing and area
Greater Productivity
Datapath Synthesis Option
Integrated transparently
Automatic partitioning of datapath and control
Automatic Operator Merging
Automatic architecture selection, creation
Enhanced component library
Integrated flow, Outstanding Results: Area, Speed
“ Development of our advanced wireless products demands high performance synthesis of complex signal processing algorithms. The Ambit BuildGates and its Datapath Option deliver outstanding results in both circuit size and speed, meeting our tough timing requirements. The Datapath option gives the obvious benefit of writing pure RTL versus instantiation of specialized datapath blocks. The significant savings in time and tool expenditures makes the Datapath option very attractive.”
Jim Nelson
Vice president of technology
LinCom Wireless
Upto 50% Area Reduction, Streamlined Flow
“ The Cadence Datapath Option has streamlined our design process, and has produced up to 50 percent reduction in datapath area. As the industry leader in support for Verilog 2000 in synthesis, Cadence makes the RTL much cleaner, smaller, and more understandable. This feature was integral in the completion of our Fast Fourier Transform (FFT) design with complex multipliers and radix-4 Butterflies.”
Raja Gosula
ASIC Manager
Innocomm Wireless
Productive Design Plan with Cadence SP&R
PKS Quick Reference Card
What is it?
A physical synthesis tool
Like conventional synthesis with superior timing-correlation and Quality of Results
Who is the Typical User
Logic designers using ASIC or COT flows
Why is it Better?
Superior correlation +/- 3%
Superior QoR & Capacity
Superior integration
PKS: What Problem Does It Solve?
DSM Timing Closure is Unpredictable
Poor correlation between Synthesis and P&R timing
Repair methods are slow to converge
SP&R Test Case 45
Video/graphics
160k instances
70 macros
5 layers, 0.18 micron
Target freq: 100Mhz
Test 45 Slack Summary
Test 45 Slack Summary
SP&R ASIC Vendor Support
SP&R Customer Adoption
SP&R Customer Adoption
Productive Design Plan with Cadence SP&R
Silicon Ensemble - PKSQuick Reference Card
What is it?
An optimization place & route tool
Like conventional P&R with superior optimizations and Quality of Results
Who is the Typical User
Digital physical designers
Why is it Better?
Superior timing and area
Signal Integrity Prevention, Analysis, and correction
Low-risk proven upgrade
Timing Closure with SE-PKS
Integration of Physical Synthesis Technology
Flow supports conventional or physical synthesis netlist or database hand-off
Preserved traditional flow steps, upgraded engines
No constraint handling issues
On-line SI technology
Clock Distribution
Clock Tree Generation
Supports gated, inverting, non-inverting, and multi-level clock trees
Clock Wire Self Heat Prevention
Inserts buffers to reduce the load
Uses wide-wire clock routing
Clock Net Hot Electron Prevention
Slew control through driver upsizing and repeater insertion
Signal Integrity
Crosstalk
Prevention
During placement optimization
Analysis and Correction
Handles both glitch and delay effects.
Post route automatic fixing
Repair Techniques
Buffer Insertion
Most cost-effective in case of congested design
Default method of fixing
Wide Space routing
Best suited for errors in non-congested areas
No penalty of logic verification (formal verification)
Shielded routing
Useful for critical nets such as Clock
Consumes routing resources
Crosstalk Results
69618 components, 43085 nets, 771 I/O pins
0.25um, 5 LM, 1.8V, 5 clocks, Max Freq - 140MHz
Power Analysis
Electromigration Analysis :
Supports comprehensive rail analysis
Clearly identify and flag segments of the rail susceptible to electromigration
Correct during the power routing phase
Voltage Drop Analysis:
Supports both static and dynamic voltage drop on the power grid
User generated vcd file input
Clearly identify and flag problem segments of the rail
Correct during the power routing
Power Analysis Results
Business StatisticsSI
Over 40 customers
More than 1000 active licenses worldwide
In use by leading ASIC vendors
Fujitsu, Hitachi, Mitsubishi, Sony, NEC, Toshiba,...
In use by leading semiconductor companies:
Cisco, Conexant, Motorola, Nortel, HP-Agilent, Texas Instruments
SI Library Characterization
Libraries Vendors - Artisan, Nurlogic, Virtual Silicon
Foundries - TSMC 0.18u, 0.15u UMC 0.15u
Other partnerships underway
Library SI cookbook available for In-house library developers
Quality of Results
Routing
Proven technology
Fastest in the industry
High density
Crosstalk repair
Antenna avoidance and repair
Supports ECO
Incremental routing
Capacity
64-bit SE-PKS
Solaris port available in May, HP port in June
Increased capacity for QP, WR, Pearl, HE
Can handle flat designs up to 10M gates
Business StatisticsP&R
Over 400 customers
More than 5000 active licenses worldwide
In use by leading ASIC vendors
Fujitsu, Hitachi, Mitsubishi, Motorola, NEC, Toshiba,...
In use by leading semiconductor companies:
IBM, Intel, Motorola, Philips, ST, Texas Instruments
Productive Design Plan with Cadence SP&R
Integration EnsembleQuick Reference Card
What is it?
A complete Front to Back, Synthesis Place & Route tool
Who is the Target Customer
Digital logical designers
Digital physical designers
Why is it Better?
Capacity/Hierarchy
Superior timing and area
Signal Integrity Prevention, Analysis, and correction
Major Features
Productive Design Plan with Cadence SP&R
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