vhdl 16位二进制计数器不能计数

vhdl 16位二进制计数器不能计数
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter16 IS
PORT(
CLK,RST,EN,SET:IN STD_LOGIC;
CHOOSE:IN BIT;
SETDATA:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
COUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END counter16;
ARCHITECTURE ONE OF counter16 IS
SIGNAL Q1:STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
PROCESS(CLK,RST,SETDATA,EN,CHOOSE,SET,Q1)
BEGIN
IF RST='1' THEN --qingling
Q1